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psoc 4 not offloading data fast enough to application.

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Hello Forum/Cypress,

I am trying to receive incoming data at the fastest possible speed.

1) I am using 2 x CYBL11573-56LQXI chips with the HCI/DTM example code.

2) The UART is set at max speed = 1Mbit.

3) The CPU clock is max speed = 48Mhz.

4) Packet Data Length extensions are enabled on both ends and packet length is MAX.

5) When receiving packets at max speed, it can be observed in-air that the device is NAK'ing packets by not incrementing the packet counter. Approximately every second packet is NAK'ed. This is usually a sign that the device cannot offload the incoming data fast enough.

This results in appox. half the speed that should be possible yielding ~15KB/sec instead of the expected ~30KB/sec.

The physical offloading of the packets to the UART does not seem to be the problem, as it never spins in the BLE_HAL_Uart_SpiUartWriteTxData() function, meaning that it never waits for room in the UART TX buffer.

However, one thing seems odd. BLE_HAL_Uart_SpiUartPutArray() is always called with 1 byte which seems inefficient. Does the whole system generate events based on 1 byte? Seems odd. I cannot see the full call stack however, as everything below is closed-source.

Anyway, is this a bug in the software or a limitation in the chip? If it is the latter it would be a pitty as Data Packet Length extensions cannot be fully utilized then.

Thanks,

/pedro


Use for status/control block in parallel in/out mode? Examples?

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Hi all,

I'm a newcomer to the PSoC 4 world, trying to learn the architecture reading the TRM (and again, and again...). One thing I don't quite get is Parallel Input / Output modes of the Status and Control Module. My understanding is as follows:

  • datapath's parallel input/output signals are available for DSI routing
  • Status and Control Module main use is to provide 8-bit registers to/from CPU part (let's ignore counter mode and interrupts for now)
  • S&C Module signals (sc_out[], sc_io_in[], sc_io_out[]) are also connected to DSI 

What I don't get is: why there is a need for "parallel output mode" (po[7:0] routed to sc_out[7:0]) and "parallel input mode" (sc_io_in[3:0] and sc_in[3:0] router to pi[7:0]). Surely one of my assumptions (probably about both pi/po and sc_* freely routable via DSI) has to be wrong...

Is there any application note explaining it in more details? Any example project using this mode?

BR,

Przemyslaw

 

 

PSoC4 and NEOWAY M590E interfacing...

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I working on program to send text message using a NEOWAY M50E modem and PSoC4. When i test run my code it works perfectly, but when i connect the modem to PSoC4, the controller doesnt receive its input asin no message is sent to the mcu. The modem is working properly cos i sent AT command to it using HTERM n it works properly. What i feel is the problem is that problem the modem is receiving or understanding its signal....

What can i do please?

PSOC 4 UART

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Im very new to PSOC. Please advice.. Thanks.

May i know how to configure UART Parity bit  in the software during runtime? 

Creating a guitar looper

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Hello!

I am very interested in creating a guitar looper. This machine will get a guitar waveform and record it and then loop the soundwave.

To do that i will have to have a SOC that has not only an ADC, as everyone has, but also a DAC (maybe 12 bit?)

Will these low cost development platforms work for this kind of application?

http://www.cypress.com/documentation/development-kitsboards/cy8ckit-043-...
http://www.cypress.com/documentation/development-kitsboards/psoc-4-cy8ck...

These two seem the same! What is the difference between them?..

Also, in their characteristics, i couldn't find if they contain DACs.

Not only that, i couldn't understand the SOC that these two had?

Is this the one? 

http://gr.mouser.com/ProductDetail/Cypress-Semiconductor/CY8C4013SXI-400...

 

Thanks a lot!

CY8CKIT-043 Pins 7[0], 7[1] are unreachable for UARTs

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It's beyond my undersanding. On the KIT UART are hard-wared to Pins 7[0], 7[1], but they are unavailable in PSoC Creator.

Changing device to another and back trick does not helps.

Where is the bug?

PSoC 4 SD Card Interface

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Hello Guys and Gals,

I'm wondering if theres a way to interface with an SD Card using SPI alone? There doesn't seem to be a nice way to do this in PSoC4.

Thanks in advance!

CAN (controller area network) register listing?

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Does anybody know if there is a document listing the controller area network(can) registers and their bit definitions?  Currently I am trying to implement canopen on a psoc4.  However I am unable to find a useful register definition document.

For reference what I have so far:

1. The "PSoC_4100M_4200M_Family_PSoC_4_Architecture_Technical_Reference_Manual_(TRM)" shows some information on CAN but it appears to be missing substantial amounts of information.  For example it shows a "CAN_RXn_ID" register but does not detail what goes into the register. Is it a function of the mail box or received can message id? If it is the received can message id is it masked or offset? It appears it is likely offset as some of its bits are reserved.

2. The "CAN_v3_0.pdf" from psoc creator appears fairly useless. Once again only some API functions are briefly detailed. It does not even detail registers directly accessed in cypresses own examples?

Any references to more detailed documents would be greatly appreciated because I am sure I must be missing something.

Thanks in advance,

Greg


CapSense Slider Design for CSD

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Hello, Community.

I have designed two CSD sensor fields.

I need round sensors, one as an endless slider like an rotary encoder.

And the other to move in menues.

Outgoing from the 10mm round buttons, I designed the two sensor fields.

So what do you think about them? Are they practicale?

Or shall I change something?

Best regards!

Jurgen

PSoC 4 Sar Mux, SampleValues differ from RealValues

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Hi,

I am new to this forum, and thought i would give it a go.

I have a problem with the Sar multiplexer on PSoC 4. The problem is that it doesnt log the actual values that i can meassure with a voltmeter. In addition, i am sampling on all 8 channels, and the offset from RealValues to SampledValues is different on each channel.

I think it might be problem with the setup of the SarMux.

Can anyone offer some insight? Something i havent thought about?

 

Note: The project is based on an SD-card example, and i have added an lcd-screen as well. Comments in code are in danish.

Purpose: The purpose of my prototype is to meassure the increase of resistance in a wire, after each bend. The PowerRelay bends the wire from side to side, and i sample each X'th cycle. I made a voltage divider to where i am meassuring the voltage after the wire i am testing, and before a 1K_ohm resistor. With Ohms law i should be able to determine the resistance of the wire by meassuring the voltage between the "two" resistors.

SampleValues:

Cycle: 0 Data: 4424, 4468, 4, 4468, 2240, 4071, 1405, 4468,
Cycle: 4 Data: 4457, 4466, 1161, 4466, 3126, 4426, 2515, 4463,
Cycle: 8 Data: 4457, 4466, 1191, 4466, 3176, 4428, 2544, 4463,
Cycle: 12 Data: 4455, 4466, 1193, 4466, 3130, 4426, 2504, 4463,
Cycle: 16 Data: 4457, 4466, 1025, 4466, 3246, 4428, 2511, 4461,
Cycle: 20 Data: 4457, 4466, 1178, 4466, 3109, 4424, 2526, 4463,
Cycle: 24 Data: 4457, 4466, 1047, 4466, 3248, 4428, 2493, 4461,

(samples in cycle 0 is the aim, and for this óne instance, was meassured correctly)

 

 

 

 

ShiftRegister to DMA issues

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I'm using a PSoC 4 BLE (CY8C4248LQI-BL583), and I'd like to copy the output of a Shift Register (v2.30) to RAM via DMA.  

The ShiftRegister does not provide a "tr_out" DMA pulse, and instead only has a level-sensitive interrupt out.  The interrupt appears to only be cleared by ShiftReg_GetIntStatus().  As such, it does not seem usable by the DMA, because the DMA event cannot clear the interrupt.

Can a ShiftRegister be hooked up to a DMA component?  The ShiftRegister documentation says yes, but I don't see how to throttle the requests without a pulsed interrupt.  Is there a ShiftRegister to DMA example out there?

 

Brian

 

 

N Element Table in Verilog, Where is it stored.

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When you define a large array of fixed 8-bit integers in verilog, where is it stored? Id like to store a table of values.

 

Thanks,

 

Nick

PSoC 4100M series programming issue

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Hello,

I'm an electrical engineering student at Arizona State University, working on a project with a team of fellow students. We choose to use PSoC in our design and have ordered the CY8C4126AXI-M443. We are implementing 3 separate MCUs in our design and we're having issues when it comes to programming them for the first time. After soldering them to our custom PCBs and doing continuity checks we power the chip with the cypress programmer from the CY8CKIT-043. On almost every chip we have tried, the select debug target window comes up. It shows the KitProg, below that instead of showing the PSoC chip it shows Cortex-M0 and gives an error on the right saying, "This device was recognized, but PSoC Creator does not support using it at this time". One of our chips programmed on the first time and had no issues, my MCU is finally being recognized and programming after updating the components in the project. We're down to our last board and we can't seem to get this one be recognized even after following the same steps we attempted that made the last chip work.

Has anyone had any issues with soldering and programming a bare chip on a custom PCB? We originally thought we fried the chips with ESD, but after de-soldering and re-soldering, we're still getting the same results. We've made new PCBs as well and thoroughly checked them for any errors in the traces and know the boards are good. At this point, I believe it's something we're not doing correctly to initialize the chip for the first time or it's something we are doing that we shouldn't. 

I'm not sure what other information I can give to help. If you need any information to better help me with this issue please ask and I'll provide it as quick as I can.

 

Thank you,

Robert Goby

unable to implement I2C protocol on CY3274

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Hi,

I am working on power line communication on CY3274 development board , and wanted to use i2c protocol to communicate with the I/O expander but unable to implement it.The problem is the chip(i.e CY8CPLC20) is unable to generate clock on SCL pin(i.e P1[7]).

Can anyone help me to solve this problem 

Regards

Shafi

unable to implement I2C protocol on CY3274

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Hi,

I am working on power line communication on CY3274 development board , and wanted to use i2c protocol to communicate with the I/O expander but unable to implement it.The problem is the chip(i.e CY8CPLC20) is unable to generate clock on SCL pin(i.e P1[7]).

Can anyone help me to solve this problem 

Regards

Shafi


UART send AT command and rcx response from MODEM

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Good day all,

I am working on project using the UART component for serial communication with the NEOWAY M590E modem. In my project i wait till the ISR receives +PBREADY before it sends any AT command. 

The issue am have is upon sending my AT command using PutString, the command is written into my array which i use to receive response from the modem. Based on my perspective the PutString function is using my isr which was connected to Rx_Int of the UART component. 

Please how do i fix this bug?

attached is a copy of my project. 

Multiple DFFs vs ShiftRegister as delay line on Routed Clock

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I have a very simple design (attached).  I'm comparing implementing a shift register (as a delay line) vs a series of DFFs.  The delay line runs off of a routed clock (asynchronous to HFCLK).

The issue I'm having is with shift register component (v2.30).  Using the shift register from a routed clock gives the warning:

Warning: sta.M0021: Design01_timing.html: Warning-1350: Asynchronous path(s) exist from "CyRouted2" to "CyHFCLK". See the timing report for details. (File=<...>\Design01.cydsn\Design01_timing.html)

In addition, the shift register does not work as expected:

  • When using the routed clock (as is in the attached project):
    • The 2-bit shift register delays the data pulse by ONE clock period (NOT EXPECTED)
    • The 2 DFFs delay the data pulse by TWO clock periods, as expected
  • If I change the routed clock to a New Clock created from HFCLK (NOT as is in the attached project):
    • The 2-bit shift register delays the data pulse by TWO clock periods, as expected
    • The 2 DFFs delay the data pulse by TWO clock periods, as expected

My misunderstanding is in how the ShiftRegister component works.  Specifically, why is it using the HFCLK at all?

Brian

 

IDAC speed improvement

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Hi guys!

How is the best possible configuration for IDAC (7 or 8 bits) and gain in PSOC-4M, in order to maximize transition speed, considering that manual just mention max 10us? If I consider an external opamp instead of a simple resistor, it may affect the performance of the IDAC?

Thanks!!

Bordi

OMG, PSoC6 is coming!

Flash Utilisation

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hi,

i am have been working on psoc-4. my flash is almost full.its about 99.1% and Sram is around 43.5%.

when i starting the program right now then its not working perfect.

but when i commented some of module and take Flash below 90% then remaining module working perfect.

so can anyone suggest me what is problem??

is that we can not use flash above 90% ?? 

 

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