Hi,
The project I am working uses ADC and demands a power save mode AND a high speed mode.
After change the clock (I am doing this through IMO reconfiguration) the ADC reads all inputs as full scale.
Is there a way to reconfigure the ADC's clock or change between the "high speed mode" and the "power save mode" without change the ADC configuration?
I am using CY8C4125.
Thanks,
Marcus
Dear All,
Im trying to write and read Flash. But it looks only reading works.
I have
/* Flash constants */
#define FLASH_ROW_SIZE_BYTES CY_FLASH_SIZEOF_ROW
#define FLASH_ALIGNED __attribute__ ((aligned (FLASH_ROW_SIZE_BYTES)))
static const uint8 FLASH_ALIGNED flashRowDataFLASH[FLASH_ROW_SIZE_BYTES]= {2}
/* Flash data write constants */
#define FLASH_DATA_BASE_ADDRESS_BYTE (uint32) (&flashRowDataFLASH)
#define FLASH_DATA_BASE_ADDRESS_ROW FLASH_DATA_BASE_ADDRESS_BYTE / FLASH_ROW_SIZE_BYTES
Read as:
a = flashRowDataFLASH[0]; and get the value 2
For write:
uint8 eepromArray[CY_FLASH_SIZEOF_ROW];
eepromArray[0] = 5;
uint8 flashWriteResult;
flashWriteResult = CySysFlashWriteRow(FLASH_DATA_BASE_ADDRESS_ROW, eepromArray);
But after a power off-on and read the value 2 is read again not 5 as expected.
Could someone tell me please what Im doing wrong ?
Thanks
Zoltan
Hi, I have a project ( fully functional) that I cretaed for CY8CKIT-042 (pioneer kit).
I would like to use it on a CY8CKIT-049-42XX ( 4$ kit).
I was thinking to simply to do a copy in creator, change target device, and recompile ...
Do I need to add a bootloader to my project?
Anything else?
Thank you
Ste
Hi,
Hopefully this is a simple question :-
The PSOC4 TCPWM block can be edge triggered or level triggered. I want to use level triggering but am struggling to find in the PSOC4 technical reference or GPIO app notes any indication as to which level(s) trigger the inputs to the block. Is it a high level, low level or both ?
Any help gratefully received
Paul.
Hi,
Have been working with the 41-40xx kit, i would like to read the voltage on the onboard potentiometer and printing the result via UART on the PC.
I'm following a code example that does this, so i created a new project and added the components on the schematic, assigned the pins, incremented heap size and placing the -u_printf_float flag on the linker, also enabling the nano lib.
Then started to write the C code but when i call the CapSense_ADC_Start() function, the project doesn't run (the red LED doesn't blink), when i comment that CapSense_ADC_Start() function the project works as expected (a blinky red LED).
I had changed the stack size to 0x200 (previously it had 0x400, the example code have 0x200).
Attached is the project if someone like to take a look and maybe spot my error.
Carlos
Hi
I have a design which is just about to be released into the wild.
Obviously I'd like the design to be protected and not readable. In the system tab of the .cydwr there is a selection for chip protection. It defaults to open but I believe I need protected - to stop others from reading/copying the device.
So I set this field to protected and programmed the PSoC4. But, I am still able to action a debug-without-reprogramming and attach-to-running-target. The debugger then allows me to read the memory. What am I doing wrong?
Ta.
Hi!
Is there anyway to have the logic blocks in a PSoc4 generate some form of hardware reset? I am using a PSoc 4200L as a keyboard controller for a project and I'd like to add a special key board combo that will trigger a (fail safe) reset if held for 4 seconds. To make this as solid as possible, I'd like to do the key detecting and counting as a logic block to be resilient to bugs in the software. Is there anyway to let the output of a logic block generate a reset? Would it be ok to route the logic block to a pin and then route the pin to XRES or should I add an external reset circuitry that makes sure to keep XRES low longer than the port output?
Are there any other ideas how this could be handled?
Best regards,
Stefan
Hi,
I started a few days using this kit and have been doing some experiments. Now I'm trying to do the example project named "OpAmp_PSoC4_Example", but I'm not getting the expected result.
In the pdf file of that example project it says that I have to "Power cycle the device". This means that I have to select the "Power cycle" programming mode in PSoC programmer?
I am only programming this kit using the onboard programmer (KitProg) and it only supports "reset" programming mode. I don't know if this is the problem and if have to get MiniProg3 (that I think it supports "power cycle" programming mode).?
PS: I am powering this kit just using the USB port.
I am working on an Android app from the ground up and currently having trouble connecting the two devices together. I am able to scan and see the PSOC 4 and it's MAC address. How do I determine the exact UUID of the PSOC 4 as a server from the PSOC Creator?
Hi!
Do the IO pins on PSOC 4200M devices have ESD clamp diodes? Where can I find information on IO pins in the M series devices?
Thank you
Hi,
I am trying to use the dual application bootload option together with the golden image support. But I am having problems getting this to work, and would like to hear if anyone has some experience with it.
My main problem is that when my custom bootloader interface is done programming, both App#1 and #2 gives error if I check with Bootloader_ValidateBootloadable. I find this strange, because I thought that when "Golden image" was enabled, App#1 should be write protected. It it the same problem if I flash "*1.cyacd" or "*2.cyacd". (I assume it should always be number 2 in my config, but a number 1 should not corrupt anything, just fail.)
Is there something I forget that I should take care of manually? As I understand it, the flash memory is split in half and when I program normally, both App#1 and App#2 is flashed with the same content. Now when an updated image arrive, my app enters the bootloader and it should try to update only App#2 and always have App#1 as a fall back option.
Any support will be appreciated, I find the documentation for multiapp and golden image a little lacking.
I tried the Ext Clock of PSoC 4 Prototyping Kits.
But, they can not work well. P0[6] works well, but other pins not work well.
do not work
http://dad8893.blogspot.jp/2016/09/psoc-4-prototyping-kitdco.html
work well
http://dad8893.blogspot.jp/2016/05/psoc-4-prototyping-kit.html
PSoC4 Prototyping kit works than P0[6]?
I want to use RTC to wake-up from sleep but after system go to sleep mode interrupt of RTC not triggered. I saw examples where WDT triggered each second but it not good decision because power consumption. I need system sleep to long time (days).
How to make it work ?
I am using the CY8CKIT-043.
The PSOC 4m device appears to have only one a/d type which is a sequencing a/d type.
I am having trouble adding more than 8 analog pins to the a/d mux. Problem is that after the 8 pin on the sequencing pin I yellow marker on the pin when I try the allocate more pins. The warning legend is reachable but will lead to routing conjestion or failure.
When two or more analog muxes are used, then the pins are allocatable, but I have not found a way to connect them to the sequencing a/d.
What I am looking for is (2) consequentive 8 analog pins where, each pin does not have external capacitors attached to the pins. Also I need 3 additional analog input pins. This leads to 19 analog inputs into the A/D.
Is this possible? A fallback position would be to have 19 analog input pins which do not have external capacitors connected to them.
Thanks.
Hi
I want to configure LM35 pin on the CY8CKIT-042-BLE.How to configure and make that work on the board?
Can i have any similar code working with the Analog pins on the BLE kit.
Regards
Srujani
Hi,
I was working with the above-mentioned kit and I succeeded a few times into downloading the firmware onto the board.
Then suddenly Bootloader Host started complaining. What does that error message actually mean?
The settings inside BH are 115200, 8, 1, None.
I have tried uninstalling the drivers using USBDeview and they were reinstalled correctly just after connecting the board.
I have PSoC Creator 4.0 on Windows XP SP3; it runs inside VirtualBox on Mac OS X El Capitan.
Hi
I am using cy8ckit -042 BLE kits and using example from the in-built examples using from PROC 4200 and selected ADC_SAR_Seq_DieTemp_PSoC4 and using the target as CYBL10563-56LQXI and giving connections from P1.5 to P12.6 and P3.0 to GND on J1.and using RS-232 with baud rate as 115200,9600,57600 and launching it on teraterm on windows 8.1 and receiving some data which is not accurate.
Please do let us know where we are going wrong.
These are the screenshots of the connections and also the RS-232.
Thanks
Srujani
I am porting a 5lp modbus device to a 4200m device. I uses the emulated eeprom component on the 5lp component. This component is not available on 4200 m device. Are there any wxamples that show writing to a flash area, that does not over write system data.
I
I recently purchased a PSOC motor control unit (CY8CKIT-037) with a PSoC 4 (CY8CKIT-042). The system comes with code to get everything up and running. I have been going through the sensored BLDC motor control code and I am a bit confused on what the timer/counter does to get the speed measurement from the hall sensors. I see that there is a count, capture, and clock input. I am not sure how the signal from the hall sensor is detected and what interval it is detected on. In addition I am confused about the difference between "on terminal count" versus "on compare/capture count". If someone can run through with me the basic functions such as how the sampling and interrupt function in this code I would be very appreciative. I have attached photos of the Timer/counter block
CY_ISR(speed_measure_isr)
{
uint16 cntCaptur = 0;
cntCaptur = Counter_Spd_ReadCapture();
speedCur = preCntCaptur - cntCaptur;
/* If speed is too low, Regard motor is stopped*/
if(speedCur > 5000) /* < 300Rpm*/
speedCur = 5000;
/* filter for speed measured */
speedCur = (preSpeedCur >> 2) + (preSpeedCur >> 1) + (speedCur >> 2);
preCntCaptur = cntCaptur;
preSpeedCur = speedCur;
Counter_Spd_ClearInterrupt(Counter_Spd_INTR_MASK_CC_MATCH);
}
Hi,
I am trying to maximise the range of our proximity sensor, and I see that AN92239 recommends the use of the ALP filter library. However when I add the code to the project, CapSense_TOTAL_PROX_SENSOR_COUNT is not defined in the source generated by the CapSense v3.0 component. With v2.40 of the component it is defined in CapSense_CSHL.h.
So that got me thinking, is the ALP filter supported by v3.0 of CapSense?
Regards,
Andy
